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This is an interesting article, I am putting it here so I don’t loose it.

It is amazing how much FPGAs have increased in speed and capacity, 1999 it took us an array of 16 FPGAs to do a fraction of what today’s low cost FPGA can do !

FPGA can be used in low latency radio interface, says Lattice – 29/04/2010 – Electronics Weekly

FPGA can be used in low latency radio interface, says Lattice

Thursday 29 April 2010 09:33

Guest columnist Ron Warner, European marketing manager at Lattice Semiconductor, looks at implementing low latency variation common public radio interfaces in an FPGA

Wireless system manufacturers are under pressure to deploy basestation architectures that have smaller footprints, consume less power, and cost less to build, deploy and operate.

Key to this is to split multiple RF transceivers and their power amplifiers from the basestation and have them directly drive their respective antennas. This is called a remote radio head (RRH).

The baseband data is transported back to the basetstation via interconnects like the SERDES-based common public radio interface (CPRI).

One needs to focus on specific low-latency variation design considerations when utilising an FPGA with an embedded SERDES transceiver and CPRI link IP.

RRH deployment context

There have been many papers written regarding the benefit of splitting the radio frequency (RF) transceiver and power amplifier from the “hotel” basestation, but most compelling are the benefits that RRHs bring to the area of power consumption, flexible deployment, smaller fixed footprint, and overall lower costs.

With the RRH decentralised from the basetstation, the operator needs to ensure that system delays between the radio head and the “hotel” basestation are calibrated. Since the delay information is used for system calibration, the entire round trip delay needs to be minimised.

This requirement is magnified with cascaded RRHs, where variations from each RRH hop are additive and the CPRI specification addresses these link timing accuracies for one way and round trip delays.

Figure 1 illustrates the key functional blocks that exist within traditional SERDES/PCS implementations and highlights the key contributors to the delay variation (RX path shown as example).

Delay variations

Delay variation can come from several components, including the analogue SERDES, digital PCS logic and the actual soft IP.

The analogue SERDES has relatively tight timing, but the word aligner and bridging FIFOs contribute large delay variations. Before suggesting a solution, it is important to understand why the aligner and FIFO contribute such a large variation.

The word aligner (top) can incur delay variations of up to 9-bit periods, depending on the initial location of the word alignment pointer within the 10-bit word.

If the 10-bit sample window captures the alignment character perfectly (item A), no delay is seen. But if the sample window is not aligned with the character, a delay of up to 9 bit periods can be incurred (item B).

Bridging FIFO

Secondly, with the hybrid architecture found in a SERDES-based FPGA, there is a need for a bridging FIFO to support the clock domain transfer from the high-speed PCS clock to the FPGA clock domain, which can introduce a delay variation of up to two parallel clock cycles.

A line rate of 2.488Gbit/s and the PCS clock running at one tenth that rate yields a clock period of around 4ns and a worse case deviation of ±8ns can be seen in each direction of the FIFO (Tx & Rx), resulting in a total variation of ±16ns.

Exacerbating the situation is when these variations are not available to the designer as they need to be compensated for at the system level to support services such as Tx diversity and GPS. The word alignment and bridging FIFOs are significant contributors to large delay variations, resulting in round trip delay tolerances exceeding the CPRI specification.

Having identified this problem, it can be addressed by making some minor changes. In certain implementations the measured latency of the word aligner in the PCS is made available via register access and the clock domain FIFO is bypassed and implemented in FPGA logic, allowing system level offsets to be applied to these delay variations.

To summarise, when this recommended implementation is used, the large components of delay variation are negated – system level offsets can be utilised to ensure predictable delays during transmission.

There are still minor delay variations through the analogue SERDES and the IP/customer design, but the overall accuracy has improved greatly, to the extent that this can now be used in multi-hop applications.

Timing now meets the round trip CPRI delay specification and is low enough to support multi-hop applications.

Wireless success story FPGAs have been part of the wireless success story for many years. From glue logic functions to more complex functions such as digital up conversion, digital down conversion, crest factor reduction and digital pre-distortion required in today’s RRH designs, FPGAs have been relied upon for their flexibility and time to market advantage.

Features such as embedded DSP blocks, embedded memory and high-speed serial I/O (SERDES) to support CPRI interconnect have dovetailed nicely with the evolving needs of wireless equipment manufacturers and basestation designers can now integrate system level functionality on a low-cost/power programmable platform such as an FPGA.